Reasons for integrated circuit package testing

With the progress of science and technology, the development of The Times, aerospace, aviation, machinery, light industry, chemical industry and other industries continue to undergo great changes, which requires the integration of integrated circuits to be higher and higher, the function is more and more complex, and want to echo the integrated circuit packaging density is also increasing.

Integrated circuit industry chain is divided into circuit design, chip manufacturing, packaging and testing three links

Integrated circuit (IC) packaging refers to the process in which the tested wafer is processed into an independent chip, which protects the circuit chip from the influence of the surrounding environment (including physical and chemical influences), and plays a role in protecting the chip, enhancing thermal conductivity (heat dissipation) performance, realizing electrical and physical connection, power distribution, and signal distribution to communicate the internal and external circuits of the chip. Compared with IC design and chip manufacturing, packaging and testing industry has the advantages of smaller investment and faster construction.

In 2011, China's IC industry achieved a sales revenue of 157.221 billion yuan, an increase of 9.2% year on year; China's packaging and testing industry sales scale was 61.156 billion yuan, accounting for 38.90% of the integrated circuit industry sales revenue, accounting for 43.69% compared to last year.

From the perspective of regional distribution of packaging and testing enterprises, the most concentrated area of packaging and testing enterprises is the Yangtze River Delta, which accounted for 55.80% of the sales revenue of packaging and testing industry in 2011, followed by Beijing-Tianjin Bohai Rim, accounting for 22.70%.

The development of integrated circuit packaging technology can be divided into four stages: the first stage: before the 1980s (jack original era), the main technology of packaging is pin insertion (PTH); Stage 2: Mid-1980s (surface mount era), lead instead of pin; The third stage: The 1990s saw a second leap into the area array packaging era. At this stage, the main packaging forms include welding ball array package (BGA), chip size package (CSP), leadless flat package (PQFN) and multi-chip component (MCM). The fourth stage: Enter the 21st century, enter the microelectronics packaging technology stack packaging era, from the original packaging components concept evolved into packaging system.

Business model. One is IDM mode, which is a wholly-owned or majority-owned packaging factory set up by an international IDM company. As a production link of the group, it is settled internally. The other is the professional OEM mode, according to the packaging amount of packaging processing fees.

Wafer-level Chip Size Packaging (WLCSP) services, compared with traditional packaging, the main difference is that the entire wafer is first packaged, tested, and then cut into the nude size of the finished chip.

The development prospect of wafer level chip size package is mainly reflected: on the one hand, the stock of image sensor chip package increases. According to the famous French market research firm

According to a research report issued by Yole Developpement, in 2007, about 35% of the world's CMOS image sensor chips used in mobile phones and laptops were packaged in wafer size, and by 2014, the vast majority of image sensor chips will be packaged in wafer size. On the other hand, the penetration of traditional packaging applications mainly includes the incremental growth of MEMS, LED and other emerging applications.